1. Field of the Invention
The present invention relates to a technique for achieving improved reliability, increased operation speed, and reduced power consumption of a static semiconductor memory.
2. Description of the Prior Art
The SRAM (static random access memory) of a CMOS (complementary metal oxide semiconductor) type having a large number of memory cells, each memory cell having a 6-transistor configuration, has been known. Each memory cell consists of a pair of P-channel MOS load transistors, a pair of N-channel MOS transfer transistors, and a pair of N-channel MOS drive transistors.
In recent years, decrease in supply voltage and shrinkage of the transistor size have been developing a tendency to decrease the drivability of each transistor of a memory cell, and accordingly, the write speed has been decreasing. As countermeasures to this problem, various techniques have been proposed for assisting the write operation of writing data in a memory cell. For example, such a write assisting technique has been known that, for the purpose of decreasing the voltage of a source power supply allocated to the pair of P-channel MOS load transistors of a memory cell only during a write cycle, the sources of the P-channel MOS load transistors are set floating (see M. Yamaoka et al., “Low-Power Embedded SRAM Modules with Expanded Margins for Writing,” ISSCC Digest of Technical Papers, pp. 480-481, February, 2005).
However, in the conventional SRAM, how much the voltage of the source power supply allocated to load transistors, for example, is decreased for assisting a write operation, and the extent of a period of executing the write assist operation, are determined in advance by simulation in consideration of a certain margin such that the normal write operation is ensured even under the worst conditions. If this margin is too large, it is possible that extravagant power consumption is required because of a charged/discharged current which is necessary for restoring the voltage to the normal level, or that a superfluous increase in driver size is required for restoring the voltage to the normal level. In the case where the write assist operation affects the retention of a memory cell in which data is not to be written, such a large margin results in decrease of the reliability.